Provides a user-friendly interface for monitoring the health status and life expectancy of a flash product.

* Compatibility and support may vary by platform or operating system.

The firmware-based power failure protection effectively protects data written to the device prior to power loss. After the host receives a signal from the device that the WRITE operation has been successfully completed, newly written as well as previously written data are protected even if a sudden power loss occurs.

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Monitors the error bit level in every operation. Before the error bit in a block reaches or exceeds the preset threshold value, AutoRefresh moves the data to a healthy block, thus preventing the controller from reading blocks with too many error bits and averting read disturbance and data corruption.

Manages the reads and writes across blocks evenly to optimize the overall life expectancy of a flash product.

Runs automatically in the background to reduce the risk of read disturbance and sustain data integrity in seldom-accessed areas by sequentially scanning the user area flag record without affecting the read/write operation. The data that has been completely moved to another block will be read and compared with the source data to ensure data integrity.

Ensures error checking and correction as data moves from the host to the storage device controller and vice versa. By covering the entire data path, end-to-end protection guarantees integrity at any point during data transfer.

As program/erase (P/E) cycles increase, memory cells age and cause voltage shifts that lead to high bit error rates (BER) when predefined read thresholds are fixed. The Auto-Read Calibration (ARC) function reduces BER and enhances reliability by adjusting/calibrating the read thresholds. ARC is supported by the TLC LDPC controller.

A sanitization solution made especially for SSDs and memory cards making sure that sensitive data is not recovered or retrieved if the SSD or memory card needs to be disposed or repurposed. By making sure that no remnant of sensitive data remains, Secure Erase is the ideal solution for government and business applications with intense security requirements.

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Operational stability in extreme temperatures from -40°C to 85°C.

Manufacturing process that encapsulates all exposed components to provide protection and shielding.

Soldered-down solutions can withstand vigorous shaking and are resistant against vibrations for reliable performance even during grueling operations.

For NAND flash storage products, the entire drive, including firmware, user and spare areas, is thoroughly tested to ensure that there are no bad blocks. DRAM products also undergo complete testing, covering PHY and controller, including meta/mapping and data caching areas.

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ATP conducts compatibility/function tests with client-supplied host devices and systems, to proactively detect and minimize failures that may not be caught in production tests, thus improving overall quality.

These modules use unique ATP testing and technologies to enable support for industrial temperature operating ranges from -40°C to 85°C but at lower price points than modules with native industrial grade ICs.

ATP DRAM modules and NAND flash storage products offer an anti-sulfur resistor option to prevent the corrosive effects of sulfur contamination, guaranteeing continued dependable performance for a long time.

Protects electronic circuits with a coating of the chemical compound Parylene to resist dust, chemical contaminants, extreme temperature, moisture and corrosion.

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Chamfering refers to the process of “beveling or tapering” the connector edges for easier insertion into the memory slots. The bevel is done at specific angles,
typically at around 40° to 50°.

30µ”-thick gold plating of the DRAM contact optimizes signal transmission quality between the connector and DRAM modules.

For NAND flash storage products, the entire drive, including firmware, user and spare areas, is thoroughly tested to ensure that there are no bad blocks. DRAM products also undergo complete testing, covering PHY and controller, including meta/mapping and data caching areas.

TDBI involves subjecting ATP DRAM modules to various temperatures, power cycling, voltages and other stress conditions within a certain period. It aims to cause weak ICs to fail so they can be screened out, thus making sure that the modules contain only the most robust ICs.

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